With the reduction of the pitches of gate electrodes, which pitches are commonly referred to as POLY pitches, increasingly more strict design rules apply. For example, for POLY pitches of 90 nm or below, fixed poly pitches are required, wherein the gate electrodes and dummy gate electrodes in a wafer are formed as parallel lines having a uniform pitch.
Under the restricted design rules, there are limited spaces for forming well pickup regions since well pickup regions are typically formed between the parallel POLY lines. The well pickup regions are necessary for the circuits. However, the well pickup regions also occupy chip areas, and it is difficult to reduce the chip area penalty resulted from the well pickup regions.